The Abaco Systems PCI-5565-010 is a reflective memory interface card enabling deterministic, low-latency data sharing across up to 256 networked nodes. The card broadcasts data written to onboard SDRAM to all connected systems transparently, eliminating host processor overhead and supporting real-time exchange between computers, workstations, PLCs, and embedded controllers regardless of architecture or operating system.
Technical Specifications
Network Architecture
• Optical ring-based topology supporting up to 256 independent nodes
• Serial connection speed: 2.12 Gbaud
• Network transfer rate: 43 Mbyte/s to 174 Mbyte/s (packet-size dependent)
• Sustained data rate: up to 170 Mbyte/s
• Deterministic latency: approximately 450 to 500 nanoseconds between nodes
Memory & Processing
• Onboard SDRAM: 64 Mbyte or 128 Mbyte configurations
• Configurable packet size: 4 to 64 bytes
• Transmit and receive FIFOs for peak-rate buffering
• One or two independent DMA channels (variant-dependent)
Physical Interfaces
• PCI bus add-in card supporting 3.3V or 5V operation
• Multimode fiber connections: up to 300 meters
• Single-mode fiber connections: up to 10 kilometers
Control & Reliability
• User-definable interrupt levels: four levels supported
• Unique node identification: 0-255 via jumper configuration
• Error detection and suppression including redundant transfer mode
• Interrupt propagation ensures reception acknowledgment before processing
– Key Features
• Software-transparent data transfer with minimal processor involvement
• Broadcast mechanism automatically replicates writes across all network nodes
• Fast local SDRAM access times for onboard storage
• Fiber-optic connectivity enables extended network distances
– Typical Applications
Real-time distributed control systems, multi-node data acquisition networks, deterministic inter-processor communication, and heterogeneous system integration requiring synchronized memory spaces.
– Compatibility & Integration
Supports PCI bus environments with 3.3V or 5V signaling. Integrates with diverse processor architectures and operating systems through hardware-based memory sharing, eliminating software protocol overhead.
