The Acromag IP-1K110-0024 is a reconfigurable FPGA IndustryPack module that implements custom logic and flexible I/O control in industrial systems. Built around an Altera EP1K100 FPGA, it allows engineers to develop and deploy their own instruction sets directly into the device via the IP bus. The module manages up to 48 TTL or 24 differential RS485 I/O signals—or any combination—with independent directional control. An internal CPLD acts as bus controller during initialization and configuration, then relinquishes control to the user-programmed FPGA. Onboard resources include 64K × 16 static RAM, a programmable interval timer, and a PLL-based clock synthesizer with external LVTTL clock input capability.
Technical Specifications
• FPGA: Altera EP1K100, FPGA-programmable via IP bus
• I/O: Up to 48 TTL signals (5V tolerant) or up to 24 differential RS485 signals, mixed configurations supported
• IP Bus: 8 MHz or 32 MHz clock frequencies
– ID space read: 0 wait states (250 ns cycle)
– Register read/write: 1 wait state (500 ns cycle)
• Memory: 64K × 16 local static RAM under FPGA control
• Clocking: Programmable PLL clock synthesizer; external LVTTL clock input routed to FPGA global clock pin
• Timers: User-programmable interval timer
• Interface: IP bus per ANSI/VITA 4-1995; supports IOSel*, IDSel*, and INTSel* cycle types
– Key Features
• TTL channels controlled in groups of 8; RS485 channels in groups of 4
• RS485/RS422 transceivers rated for 32-node networks, 4000 feet cable distance
• Pre-programmed CPLD manages power-up sequence and bitstream download
• VHDL reference design provided for IP bus interface
– Typical Applications
Specialized communication systems, test fixture simulation, and adaptive computing requiring custom mathematical processing or protocol implementation.
– Compatibility & Integration
Standard single-size IndustryPack form factor. Compliant with ANSI/VITA 4-1995 specification.
