The Curtiss-Wright IXZ1644-0-B3110 is a 6U VME real-time multiprocessing board delivering 1.9 GFLOPS peak performance through 16 SHARC DSP processors. Engineered for mission-critical systems and harsh-environment deployment, this board combines exceptional processing density with flexible memory architecture and modular I/O configuration.
## Technical Specifications
**Processing Architecture**
• 16 SHARC DSP processors (ADSP21060) organized in 4 clusters of 4 processors each
• Peak processing power: 1.9 GFLOPS
• Advanced Multichip Module (MCM) packaging with Ball Grid Array (BGA) technology developed with Analog Devices, Inc.
**Memory Subsystem**
• Local cluster memory: Up to 2 MB of 0ws SRAM per cluster (8 MB total)
• Global memory (IXQ1): Up to 128 MB DRAM, accessible to all four clusters and VME interface; includes fast auxiliary dual-ported VME memory
• Shared memory (IXQ2): Up to 128 MB DRAM, accessible to two clusters
• Total capacity: 256 MB DRAM and 8 MB SRAM
**Interconnectivity**
• 16 offboard SHARC IXLink ports at 40 MB/s each (640 MB/s aggregate interprocessor bandwidth)
• Integrated Board Controller decouples SHARC clusters from VME and host systems
• MultiProcessor Resource (MPR) for control and coordination across multiple IXZ boards
**I/O Configuration**
• Two IXI Mezzanine slots supporting modular, high-speed signal I/O
• Flexible personality module for P2 interconnection
• Single 6U VME slot accommodates dual mezzanine installation
## Key Features
• High processing density through MCM/BGA architecture
• Decoupled cluster management reduces host and VME overhead
• Scalable multiboard coordination via MPR
• Configurable analog or digital signal acquisition and processing
## Typical Applications
Signal processing, real-time data acquisition, multiprocessor system integration, and demanding computational workloads in defense, aerospace, and industrial control environments.
## Compatibility & Integration
VME-based systems with support for IXI mezzanine I/O modules and multi-board cluster expansion through the MultiProcessor Resource architecture.
