The Tektronix BSA286CL BERTScope is a high-performance Bit Error Rate Analyzer engineered for validation testing of serial data links operating from 1 Gb/s to 28.6 Gb/s. It combines pattern generation, error analysis, and eye diagram characterization to deliver rapid BER measurement and signal integrity diagnostics across communication systems and high-speed device validation.
Technical Specifications
Data Rates & Clocking
• Data rate range: 1 Gb/s to 28.6 Gb/s
• Clock outputs: 1 GHz to 28.6 GHz
• Sub-rate clock outputs: 0.250 GHz to 3.575 GHz (standard); extends to 8.5 GHz with optional Stressed Signal Generation (STR)
Jitter Analysis
• Measurements: Total Jitter (TJ), Random Jitter (RJ), Deterministic Jitter (DJ) per MJSQ methodology
• Sinusoidal Jitter (SJ): 1 kHz to 100 MHz internal frequency range
• Additional capabilities: Random Jitter (RJ), Bounded Uncorrelated Jitter (BUJ), Sinusoidal Interference (SI) generation and analysis
• Jitter decomposition with optional Jitter Map, including jitter triangulation for subcomponent analysis
• Spread Spectrum Clocking (SSC) with adjustable modulation; Extended SSC (XSSC) available via STR option
• F/2 jitter generation for 8xFC and 10GBASE-KR testing
Pattern Generation & Error Analysis
• Hardware patterns: PRBS sequences (2ⁿ-1 where n = 7, 11, 15, 20, 23, 31)
• RAM patterns: 128 bits to 128 Mb (allocated in 32 Mb portions across two A/B pages)
• Pattern library: SONET/SDH, Fiber Channel (k28.5, CJTPAT), 2ⁿ patterns (n=3,4,5,6,7,9), Mark Density patterns
• Error insertion: Burst widths of 1, 2, 4, 8, 16, 32, or 64 bits in single or repetitive modes
• Error Location Analysis™: Patented deterministic versus random error assessment with pattern-dependent error analysis
– Key Features
• Eye diagram analysis with sophisticated signal integrity assessment
• Jitter tolerance templates: standard or user-defined libraries
• Optional STR suite: ECC emulation, MAP (Error Mapping Analysis), Physical Layer Test Suite (PL), XSSC, and JTOL templates
– Typical Applications
High-speed serial link validation, communication system characterization, device performance qualification, jitter tolerance compliance testing.
– Compatibility & Integration
Supports standard jitter measurement methodologies and optical/electrical serial data protocols across telecommunications and enterprise standards.
