The Tektronix BSX320 BERTScope is a protocol-aware Bit Error Ratio Analyzer designed for characterization and validation of high-speed serial data links up to 32 Gb/s. This instrument accelerates debugging of physical layer and link training issues while validating compliance with Gen3 and Gen4 standards including PCIe, SAS, SAS/SATA, USB 3.1, and DisplayPort.
Technical Specifications
• Data rate: Up to 32 Gb/s for pattern generation and error analysis
• Standards support: Gen3 and Gen4 protocols (PCIe, SAS, SAS/SATA, USB 3.1, DisplayPort, proprietary standards)
• Protocol-aware handshaking and synchronization with device under test
• DUT handshaking capability above 16 Gb/s for RX test requirements, including loopback initiation and adaptive link training
• 4-tap transmit equalization (optional)
• Jitter analysis from 1.5 to 32 Gb/s with random jitter up to 0.5 UI, band-limited 10 MHz to 1 GHz (1.5 MHz to 100 MHz in PCIe2 mode)
• BER-based direct Total Jitter measurement to 10⁻¹² BER and beyond
• Jitter decomposition: random jitter, bounded uncorrelated jitter (BUJ), data dependent jitter (DDJ), inter-symbol interference (ISI), duty cycle distortion (DCD), sub-rate jitter (SRJ)
• Eye diagram analysis with BER correlation, mask testing, and BER contour
• Optional jitter map for comprehensive decomposition including long patterns (PRBS-31)
– Key Features
• Protocol-oriented and bit-oriented multi-chain pattern sequencing with enhanced pattern/sequence editor
• User-defined detector pattern matching with stimulus-response feedback
• Optional forward error correction (FEC) analysis with post-FEC error rate simulation
• Patented Error Location Analysis for deterministic error pattern correlation
• Stressed signal generation (STR) for stressed receiver sensitivity and clock recovery jitter tolerance testing
• Spread spectrum clocking (SSC) measurement and display with frequency deviation and modulation rate analysis
– Typical Applications
Physical layer validation, link training debugging, receiver sensitivity characterization, clock recovery jitter tolerance assessment, and compliance verification for high-speed serial standards.
