The NI PXI-1042 is an 8-slot, 3U PXI chassis engineered for modular test and measurement systems requiring high-performance signal distribution and synchronized timing. This chassis accepts both 3U PXI and CompactPCI modules, delivering 132 MB/s maximum system bandwidth across a CompactPCI 64-bit compliant backplane. The design emphasizes maintainability through modular construction while supporting up to 25 W per slot thermal capacity.
Technical Specifications
• Slots & Backplane: 8-slot, high-performance PXI backplane; 132 MB/s maximum system bandwidth
• Module Compatibility: 3U PXI and CompactPCI modules
• Specification Compliance: PXI Specification Revision 2.0; CompactPCI 64-bit specification
• Thermal: 25 W per-slot cooling capacity
• Triggering: 8 shared PXI trigger lines; support for PXI trigger bus, star trigger, and local bus
• Reference Clock: Built-in 10 MHz at 25 ppm accuracy with <5 ps jitter; 250 ps slot-to-slot skew. External 10 MHz clock input via BNC IN with automatic switchover; buffered output available on BNC OUT. Optional NI PXI-6653 module (slot 2) enables 50 ppb accuracy with <0.1° phase mismatch.
• Power Supply: 300 W universal AC, 100–240 VAC input, 90–264 VAC operating range, 50/60 Hz. 10 A circuit breaker; isolated 12 VDC fan line. Output regulation: +3.3 V (±0.2% line, <5% load), +5 V (±0.1% line), ±12 V (±0.1% line). Ripple/noise: +3.3 V @ 50 mVpp maximum. 70% typical efficiency.
• Remote Control: D-SUB 9-pin rear connector for power inhibit and voltage monitoring
• Physical: 6.97 × 10.68 × 15.61 inches; 18.6 lbs. 4U rack-mount height with optional front/rear kits for 19-inch racks.
– Key Features
• Removable, high-performance AC power supply unit
• Front-panel power switch with error indication (flashing red LED)
• P1 connector (CompactPCI standard); P2 connector (PXI-specific signals)
• Conductive clear Iridi chassis material
– Compatibility & Integration
Interoperable with standard CompactPCI and PXI-compatible modules. Supports synchronized multi-slot configurations via PXI trigger lines and shared reference clock distribution.
