The Curtiss-Wright/VMETRO Vanguard VG-VME Bus Analyzer delivers real-time protocol analysis and debugging for VMEbus systems. It captures and displays complete bus activity across all VME standards, executing advanced triggering, filtering, and statistical measurements from a networked PC interface. Designed for software developers, system integrators, and hardware designers, the analyzer identifies protocol errors and optimizes system performance through state and timing analysis with synchronized sampling.
## Technical Specifications
• **Bus Support:** VME, VME64, 2eVME, 2eSST
• **Trace Buffer:** 2M Sample at 256-bits width
• **Analyzer Modes:** State Analyzer and 133 MHz Timing Analyzer
• **Trigger Sequencer:** 16-Level with 8 Events of 256-bits; operators include IF, ELSIF, ELSE, STORE, COUNT, DELAY, GOTO
• **Transaction Support:** All VMEbus transactions (2eSST, VME64, IACK, RMW) with full 64-bit Address/Data demultiplexing
• **Interfaces:** 10/100 Mbit/s Ethernet and USB
• **Control:** Windows-based BusView GUI via USB or Ethernet
• **Power:** External supply; source selectable from target system or independent supply
• **Test Connectivity:** BNC trigger output, USB cable, Ethernet cable, pin header patch leads, micrograbber clips
## Key Features
• Multi-level Trace Viewer for customized data analysis and protocol-aware waveform interpretation
• Integrated Ethernet port enables remote analyzer access across networked locations
• Independent Real-time Statistics Engine performing concurrent Event Counting, Bus Utilization, Transfer Rate, Block Length Distribution, Arbiter Latency, and User-Defined measurements
• Sophisticated trigger and store qualifiers with inside/outside range specification on address, attribute, and data fields
• Full visibility into Interrupt Request and Interrupt Acknowledge cycles within trace listings
• Optional Exerciser operating as VMEbus Master with dual DMA engines for extensive test generation
## Typical Applications
Protocol verification, arbitration and block cycle analysis, interrupt sequence debugging, RMW operation validation, and statistical bus performance characterization.
## Compatibility & Integration
Supports current and legacy VME implementations across 32-bit and 64-bit address spaces with protocol-synchronized sampling for accurate bus cycle correlation.
