The Mercury Computer Systems RACE MCJ6 is a 6U VME64 motherboard engineered to host RACE++ daughtercards for high-performance embedded computing and real-time processing. The board accommodates two daughtercards supporting up to four compute nodes total, with each node connected via a RACE++ crossbar switch fabric delivering 267 MB/s per connection and peak aggregate bandwidth exceeding 1 GB/s. Initial crossbar connection latency is 75 ns, dropping to 15 ns once established. The MCJ6 integrates a Tundra Universe II VME/PCI bridge and Mercury PXB++ PCI-to-RACEway bridge, supporting the full VME64 transfer mode set with 160-pin VME64x connectors (VITA 1.1-1997 compatible). Optional 96-pin connector support draws 5 V from the VME backplane without requiring 3.3 V. When configured with FPGA Compute Nodes, each board hosts two Xilinx Virtex-II Pro FPGA nodes (7 million gates each), each backed by 8 MB QDR II SRAM with 6.4 GB/s peak access and 128 MB RLDRAM II staging capacity. The two FPGAs communicate over ten 2.5 Gbps serial links and support real-time reconfiguration with bitstream loads completing in under 100 ms. The motherboard also supports processor daughtercards including SHARC DSP, PowerPC, and PowerPC 7400/7410/750 variants, enabling mixed-processor architectures across multiple boards via RACEway Interlink connectivity.
Technical Specifications
• Form Factor: 6U VME64
• Part Number: 910-08000
• Switch Fabric: RACE++ crossbar with 267 MB/s per connection; four simultaneous paths yielding >1 GB/s peak bandwidth
• Latency: 75 ns initial connection; 15 ns established
• Daughtercard Slots: Two RACE++ slots (up to four compute nodes total)
• VME Interface: VME64 via Tundra Universe II bridge; 160-pin VME64x or optional 96-pin connectors; 5 V backplane draw
• FPGA Node (per board): Two Xilinx Virtex-II Pro FPGAs (7M gates each)
• FPGA Memory: 8 MB QDR II SRAM per FPGA (6.4 GB/s peak); 128 MB RLDRAM II staging per FPGA
• Inter-FPGA Links: Ten 2.5 Gbps serial connections per board pair
• Bitstream Load Time: <100 ms
– Key Features
• Support for mixed RACE++ and RACE 1.0 daughtercards
• Intermixable with MCH Series motherboards
• Compatible with SHARC DSP, PowerPC, and PowerPC processor families
• Mercury-provided IP for RACE++ fabric interface and memory control
• RACEway Interlink for multi-board scalability
– Typical Applications
Real-time signal processing, high-throughput data acquisition, reconfigurable computing, and multiprocessor embedded systems requiring sub-microsecond latencies and gigabit-scale bandwidth.
– Compatibility & Integration
Full VME64 ecosystem integration; interoperable with RACE Series I/O devices; developer FPGA Development Kit (FDK) available with fabric interface and I/O management IP.
