The NI VXIpc-650B/233 is a B-size Pentium-based VXI controller that embeds directly into VXI and VME mainframes to provide PC-compatible system control and high-speed data acquisition. Built around a 233 MHz Pentium MMX processor, this controller delivers full VXI and VME functionality with direct register, memory, interrupt, and trigger management through a high-performance backplane. The architecture combines x86 processing with PCI bus connectivity and custom DMA ASICs for block-mode data transfer, making it suitable for demanding real-time control and signal processing tasks in modular instrumentation systems.
Technical Specifications
• Processor: 233 MHz Pentium MMX
• Memory: 16 or 32 MB SDRAM (default); upgradeable to 128 MB SDRAM maximum
• Form Factor: B-size; occupies two B-size slots in VXI or VME mainframe
• Bus Architecture: x86 processor with PCI bus
• Clock Signals: 16 MHz VXI/VMEbus system clock from onboard oscillator; 10 MHz CLK10 differential ECL output when installed in Slot 0
• Custom ASICs: MITE and MANTIS for high-performance DMA block-mode transfers; TNT4882C for GPIB control
• Interfaces: Ethernet, GPIB, IEEE 488.2, SCSI, IDE hard drive, SuperVGA, 3.5″ floppy, LPT, serial, PS/2, USB, and two SMB trigger I/O connectors (TTL)
– Key Features
• Full VXI slot control with automatic system controller detection; can be deployed in any slot or configured as non-system controller
• Generates and distributes CLK10 signal for multi-mainframe synchronization
• VXIplug&play compliant with support for NI-VXI, NI-VISA, and NI-488.2 software stacks
• Compatible with LabVIEW and LabWindows/CVI development environments
• Supports Microsoft Windows 95/NT and VxWorks operating systems
• Direct VXI register access and interrupt/trigger routing through interactive utilities and C function calls
– Compatibility & Integration
Installs in VXI and VME mainframes with native support for full VME functionality. Slot 0 installation enables system controller duties and CLK10 generation; external CLK10 connector accommodates distributed clock architectures across multiple mainframes.
