The Keysight N4916B is a de-emphasis signal converter that enables accurate characterization of high-speed serial interfaces by emulating transmitter de-emphasis at the front end of pattern generators. It compensates for signal distortions introduced by transmission media, cables, fixtures, and test boards—critical for receiver tolerance characterization in multi-gigabit applications.
The N4916B generates 4-tap de-emphasis with one pre-cursor and two post-cursors, each with individually adjustable levels ranging from 0 to 12.0 dB. This architecture mirrors real-world transmitter behavior and allows optimization of jitter budgets during compliance testing. The converter operates across data rates from 660 Mb/s to 14.2 Gb/s, making it suitable for PCI Express, USB 3, SATA, and IEEE 802.3 backplane standards.
Technical Specifications
• De-Emphasis Configuration: One pre-cursor and two post-cursors with independent level adjustment
• De-Emphasis Range: 0 to 12.0 dB per tap
• Data Rate Support: 660 Mb/s to 14.2 Gb/s
• Jitter Transparency: Maintains jitter characteristics from source pattern generator on both data and clock paths
• Pattern Tolerance: Accepts non-balanced patterns via DC coupling
• Control Interface: USB programmable via J-BERT N4903B user interface or standalone control
• Interconnect: Matched cable pair (N4915A-010) for DATA IN/OUT and CLK IN/AUX CLK OUT
• Termination Requirement: Unused pattern generator DATA OUT ports require 50 Ω termination
– Key Features
• Transparent to jitter on data and clock signals
• Compensates for channel, cable, fixture, and test board degradation
• DC-coupled architecture for non-balanced pattern support
• Optional clock multiplier (Option 001) for half-rate clock device analysis and full-rate error/eye/jitter measurement
– Typical Applications
• Multi-gigabit serial interface characterization (5 Gb/s and above)
• Receiver compliance and tolerance testing
• Transmitter de-emphasis emulation and validation
• Channel loss compensation in high-speed digital testing
– Compatibility & Integration
Designed as a front-end module for the Keysight J-BERT N4903B pattern generator and ParBERT 81250A. Integrates directly between pattern generator DATA OUT and device under test, with auxiliary clock connection from pattern generator AUX CLK OUT.
