The Anritsu MP1763C is a pulse pattern generator operating from 0.05 GHz to 12.5 GHz, delivering data rates up to 12.5 Gbit/s for high-speed digital communication system validation. It generates alternate, programmable, zero substitution, and pseudorandom binary sequences (PRBS 2^7–1 to 2^31–1) with programmable pattern memory up to 8 Mbits. Output amplitude ranges from 0.25 Vp-p to 2 Vp-p in 2 mV steps, with VOH adjustable from –2 V to +2 V in 1 mV increments. The instrument delivers rise/fall times below 30 ps (typical), crossover jitter less than 20 ps p-p, and Q factor exceeding 40 dB at 10 Gb/s. Data and clock outputs feature back termination to minimize waveform distortion to ≤15% or ≤150 mV. With Option 01, the internal clock generator provides frequency resolution in 1 kHz units across the full 50 MHz to 12.5 GHz band, with SSB phase noise ≤–85 dBc/Hz (0.05–4 GHz), ≤–80 dBc/Hz (4–8 GHz), ≤–75 dBc/Hz (8–10 GHz), and ≤–70 dBc/Hz (10–12.5 GHz) at 10 kHz offset.
Technical Specifications
• Frequency Range: 0.05 GHz to 12.5 GHz
• Maximum Data Rate: 12.5 Gbit/s
• Output Amplitude: 0.25 Vp-p to 2 Vp-p (2 mV steps)
• VOH Adjustment: –2 V to +2 V (1 mV steps)
• Rise/Fall Time: <30 ps (typical)
• Crossover Jitter: 40 dB; 40 dB typical at 10 Gb/s (PRBS 2^23–1)
• Pattern Memory: Up to 8 Mbits programmable; supports six STM-64 frames
• PRBS Patterns: 2^7–1 to 2^31–1 selectable
• Internal Clock Option 01 Phase Noise: ≤–85 dBc/Hz (0.05–4 GHz), ≤–80 dBc/Hz (4–8 GHz), ≤–75 dBc/Hz (8–10 GHz), ≤–70 dBc/Hz (10–12.5 GHz) at 10 kHz offset, 1 Hz bandwidth
– Key Features
• Alternate, programmable, zero substitution, and PRBS pattern generation
• Back-terminated DATA and DATA complementary outputs
• Three clock outputs: CLOCK1, CLOCK1, and CLOCK2
• 1/8 parallel output standard configuration
• Pattern input via front panel, GPIB, or 3.5-inch floppy disk (2HD, 2DD, MS-DOS)
• Internal clock with 1 kHz frequency resolution (Option 01)
• Low FM/PM-noise clock generation
– Typical Applications
• Bit Error Rate testing (BERT) paired with MP1764C or MP1764D detectors
• STM 0/STS1 through 10 GbE validation
• STM64/STS192 and OTU-2 system testing
• 4.25 Gbit/s Fibre Channel subsystem characterization
• High-speed digital electronics research and manufacturing test
– Compatibility & Integration
Forms a complete BERT solution when paired with compatible Anritsu error detectors (MP1764C, MP1764D) for signal integrity verification and system reliability assessment.
