The Anritsu MP1764A is a high-performance error detector designed for testing high-speed digital communication systems and semiconductors. It is engineered to work in conjunction with a pulse pattern generator, such as the Anritsu MP1763B or MP1763C, to evaluate conformity with ITU-T standards and perform bit error rate testing (BERT). The MP1764A is characterized by its ability to simplify complex threshold and phase adjustments with single-key operations, making it suitable for research and development of ultra-high-speed logic ICs and digital communication systems.
## Technical Specifications
### General
* **Product Name:** Anritsu MP1764A Error Detector
* **Supported Systems:** High-speed digital communication systems, high-speed semiconductors, ultra-high-speed logic ICs.
* **Primary Application:** Bit Error Rate Testing (BERT), evaluation of conformity with ITU-T standards.
### Electrical Specifications
* **Operating Frequency Range:** 0.05 GHz to 12.5 GHz
* **Input Waveform:** NRZ (Non-Return-to-Zero)
* **Input Voltage:** 0.25 to 2.0 Vp-p
* **Input Sensitivity:** 50 mVp-p (typical value at 10 Gb/s, PRBS 2^23 – 1)
* **Threshold Voltage Variable Range:** –3.000 Vp-p to +1.875 Vp-p (in 1 mV steps)
* **Phase Margin:** ≥ 70 ps (typical value at 10 Gb/s, PRBS 2^23 – 1, and an input amplitude of 1 Vp-p)
* **Termination:** 50 Ω connected to GND (excluding ECL) or to –2 V (ECL)
### Clock Specifications
* **Input Delay Variable Range:** –500 ps to +500 ps (in 1 ps steps)
* **Polarity Inversion:** CLOCK/CLOCK inversion is possible.
* **Termination:** 50 Ω connected to GND (excluding ECL) or to –2 V (ECL)
* **Connector:** APC-3.5
### Data and Pattern Generation
* **Supported Patterns:**
* Pseudorandom Binary Sequence (PRBS) Pattern: 2ⁿ – 1 (n = 7, 9, 11, 15, 20, 23, 31)
* Programmable (PRGM) Pattern: Maximum 8 Mbits (capable of programming six STM-64 (OC192) frames)
* Alternate Pattern
* Zero Substitution Pattern
* **Mark Ratio Settings:** 1/2, 1/4, 1/8 (possible with logic inversion for 1/2, 3/4, 7/8, 8/8).
* **AND Bit Shift (Mark Ratio Setting):** 1 or 3 bits (selectable via DIP switch on rear panel).
* **Data Length (Receive):** 2 to 8,388,608 bits
### Interfaces
* **Data Input/Output Connectors:** APC-3.5
* **Clock Input Connector:** APC-3.5
* **GPIB Ports:** Two GPIB ports (GPIB 1 for remote control, GPIB 2 for external printer control) supporting IEEE 488.2.
### Functions
* **Auto-Search Function:** For setting optimum input threshold and phase automatically with a single touch.
* **Error Detection Modes:**
* Total Error
* Insertion Error
* Omission Error
* **Synchronization:** Capable of synchronizing 8 Mbits pattern in a short period (in frame mode).
* **Zero Wait Time Counter Gate:** Available.
* **Error Location Analysis:** Available (with Option 01).
### Physical Specifications
* **Weight:** Approximately 66.00 lbs (30 kg)
* **Dimensions:** 426 mm (Width) x 221 mm (Height) x 450 mm (Depth) (approximate)
### Compatibility
* **Primary Companion Instrument:** Anritsu MP1763B Pulse Pattern Generator, Anritsu MP1763C Pulse Pattern Generator.
Why Choose Aumictech for Anritsu MP1764A?
At Aumictech, we specialize in supplying high-end test and measurement equipment. Whether you need precise error detection for high-speed digital communication systems, reliable evaluation for ITU-T standard conformity, or simplified phase and threshold adjustments for R&D of advanced ICs, our team ensures the Anritsu MP1764A delivers maximum performance for your application.
