The Acromag IP341 is a 14-bit simultaneous analog input module delivering high-resolution data acquisition across 16 differential channels in industrial environments. Eight integrated 14-bit ADCs enable true simultaneous sampling of paired 8-channel banks, with conversion completed in 8 µS per bank or 16 µS for all 16 channels. Maximum throughput reaches 1 MHz across all 16 channels, supporting demanding signal measurement and logging applications requiring precision and speed.
Technical Specifications
Analog Input Channels
• 16 differential inputs, ±10V DC range
• 14-bit resolution with 2.4 LSB accuracy (0.014%)
• Simultaneous sampling via dual 8-channel banks
• Conversion time: 8 µS per bank, 16 µS for complete 16-channel cycle
• Maximum throughput: 125 kHz single channel; 1 MHz for 8-channel bank or all 16 channels
• Input overvoltage protection: ±25V powered, ±40V unpowered
• Common mode rejection (60 Hz): 96 dB typical
• Channel-to-channel rejection (60 Hz): 96 dB typical
• Data format: Binary two’s complement
Data Acquisition
• 512-sample FIFO buffer with data tagging
• Conversion modes: Continuous and single-cycle
• Programmable timer: maximum 2.09 seconds interval
• Individual channel/bank enable/disable control
• Trigger sources: Internal timer, external TTL, software
• Interrupt generation on FIFO threshold conditions
– Key Features
• Eight simultaneous 14-bit ADCs eliminate phase skew between channels
• TTL-compatible external trigger input/output
• Programmable per-channel conversion control for flexible acquisition patterns
• Tagged FIFO data simplifies multi-channel signal identification
– Typical Applications
Multi-channel industrial data logging, transducer arrays, vibration monitoring, precision instrumentation, and distributed sensor networks requiring synchronized sampling.
– Compatibility & Integration
Industry Pack module compatible with VMEbus carriers (AVME9670, AVME9630/9660) and PC/AT PCIbus (APC8620). Double-height 6U single-slot VME64x form factor. Standard IOSel* and IDSel* data transfer cycles with typical 0–1 wait states at 8 MHz clock.
