The Tektronix PPG3002 is a 2-channel programmable pattern generator delivering data rates up to 30 Gb/s for high-speed digital communication and semiconductor testing. Built-in PRBS and user-defined pattern generation enable comprehensive stimulus capability, while integrated jitter insertion (BUJ, SJ, RJ, PJ) simulates real-world signal degradation. Multi-channel synchronization maintains pattern-independent alignment across outputs, essential for complex receiver characterization and BER analysis.
Technical Specifications
• Data Rate: Up to 30 Gb/s
• Channels: 2
• Output Amplitude:
– Single-ended: 300 mV to 1.0 V or 250 mV to 2.0 V
– Differential: 600 mV to 2.0 V or 500 mV to 4.0 V
• Offset Window: Programmable −2 V to +3 V
• Rise/Fall Time: 11 ps (20%–80%), 16 ps (10%–90%)
• Output Impedance: 50 Ω single-ended, 100 Ω differential, 50 Ω DC-coupled differential
• Data Output Jitter: 250 fs RMS RJ typical at 30 Gb/s (PRBS 2^11-1); 900 fs RMS typical (PRBS 27-1)
• Channel Skew Adjust: ±50 ps range, 100 fs resolution
• Pattern Shift: ±(2^30-1) range, 1 bit resolution
• Error Insertion: Single or rate-based, 1×10^-3 to 1×10^-15 BER, 3 digits resolution
• Clock Input: 15 GHz to 30 GHz
• Reference Clock I/O: BNC connector
– Key Features
• Front-panel touchscreen GUI and USB TMC control
• 2.4 mm data output connectors
• Pattern-independent multi-channel synchronization
• Configurable jitter insertion for receiver stress testing
• Compact rack-mount form factor: 45.1 cm W × 13.3 cm H × 35.1 cm D; 11.1 kg
– Typical Applications
• 100G Ethernet multi-channel 25 Gb/s testing
• DQPSK and DP-QPSK modulation validation
• PAM4 and multi-level signal characterization
• CFP2 and CFP4 transceiver testing
• 32G Fibre Channel receiver qualification
• Semiconductor and component validation
– Compatibility & Integration
Integrates with Tektronix PED series Error Detector products for complete bit-error-rate measurement capability.
