The Tektronix HFS9003 Programmable Stimulus System is a VXIbus-compliant, modular mainframe designed to generate high-speed electrical stimulus signals for semiconductor device characterization. The C-size mainframe accommodates a CPU card, time base card, and up to three pulse or data generator cards, delivering up to 12 channels of stimulus with optional configurations supporting 640+ phase-locked channels. Built on fully digital architecture, the system characterizes CMOS, ECL, ACL, BiCMOS, and GaAs devices with 1 ps timing resolution and independent edge placement on every pin.
Technical Specifications
• Frequency Range: 50 kHz to 630 MHz
• Frequency Resolution: <0.1% of programmed value
• Frequency Accuracy: ±1% of programmed value
• Repetition Rate: Up to 630 MHz
• Timing Resolution: 1 ps
• Channel Deskew Range: −60 ns to 2.0 µs with 1 ps resolution
• Delay Adjustment: 0 to 20 µs range, 1 ps resolution, 1% ±50 ps accuracy
• Pulse Width Adjustment: 0 to 65,536 × one period, 1 ps resolution
• Output Transition Time (20%–80%): <250 ps for <1 V p-p; variable 800 ps to 6 ns
• RMS Jitter: 15 ps ±0.05% of interval
• Phase Lock In Range: 6 MHz to 630 MHz input frequency, 0.8 V to 1.0 Vp-p amplitude
• Output Level Resolution: 0.01 V
• High Level Accuracy: ±2% of level ±50 mV
• Low Level Accuracy: ±2% of HIGH level ±2% of amplitude ±50 mV
• Output Aberrations (200 ps after 50% point): Overshoot +15% +20 mV; Undershoot −10% −20 mV
– Key Features
• Modular VXIbus architecture with upgrade capability
• Fully digital signal generation and control
• Independent edge placement for precise per-pin timing
• Channel-to-channel timing alignment to 1 ps
• External PHASE LOCK IN reference with FRAME SYNC IN burst initiation
• HFS 9DG1 and HFS 9DG2 generator card support
– Typical Applications
• Semiconductor device characterization and validation
• High-speed digital stimulus pattern generation
• Clock and timing signal generation
• Multi-channel synchronization testing
– Compatibility & Integration
VXIbus card-modular C-size mainframe with CPU, time base, and data generator card slots.
